1. Field of the Invention
The present invention relates to devices and methods for making semiconductor devices, and in particular to a device and method for making monolithic bypass-diodes and solar-cell string assemblies.
2. Description of the Related Art
Solar cells are used in various technologies to provide power to other electronic assemblies. Satellites, calculators, and power systems are all examples of solar cell usage.
A solar cell is a p-n junction created over a large area on a semiconductor substrate. Solar cells are typically long-life devices, but can have their efficiency reduced or destroyed by reverse biasing of the solar cell junction. To prevent this type of damage, bypass diodes (BDs) are used to allow current to flow in an anti-parallel direction to the current flow through the solar cell junction.
Bypass diodes are typically formed using an isolated island structure and/or created in a recess of the back (reverse) of the solar cell substrate, and connected to the solar cell using additional wiring and/or additional metallization on the solar cell substrate. The use of additional wiring and/or additional metallization creates new failure points for solar cells, as well as adding to the weight and complexity of the solar cell structure. Additional weight and failure mechanisms are unacceptable in a spacecraft environment, because of the extreme additional costs involved. Further, additional metallization obscures the solar cell from receiving incident light, which reduces the efficiency of the solar cell structure.
FIGS. 1A-1B illustrate a related art device that integrates bypass diodes with solar cells.
FIG. 1A illustrates a cross-sectional view of a semiconductor device. Assembly 100 comprises solar cell 102 and bypass diode 104. Solar cell 102 utilizes an n-doped substrate 106 and a coupled p-doped layer 108. Substrate 106 and layer 108 are coupled electrically, such that a depletion layer is created between substrate 106 and layer 108. The method of coupling can be, for example, deposition of layer 108 on substrate 106, diffusion of p-type carriers into substrate 106 to form layer 108, chemical vapor deposition of layer 108, epitaxial growth of layer 108 on substrate 106, or other methods.
Bypass diode 104 utilizes a p-doped layer 110 and an n-doped layer 112 to create a separate p-n junction. Layer 110 is electrically coupled to substrate 106, and is isolated from layer 108 by a dielectric isolation layer 114. External connections 116 and 118 are complemented by metallization connections 120 and 122 to create the solar cell/bypass diode assembly 100. A more extensive description of the device illustrated in FIG. 1A can be found in U.S. Pat. No. 4,759,803, issued Jul. 26, 1988, which is herein incorporated by reference.
FIG. 1B illustrates a schematic diagram for assembly 100. Bypass diode 104 and solar cell 102 are connected in an anti-parallel configuration, with external connections 116 and 118 shown, in order to connect the assembly 100 to other assemblies 100.
The limitations of the assembly 100 shown in FIG. 1A is that there is a third p-n junction in the assembly, namely, that created by the coupling of layer 110 and substrate 106. Further, the active area of the solar cell 102, shown as area 124, is reduced by the physical size of isolation layer 114 and the presence of bypass diode 104. Since the active area 124 of the solar cell is smaller than without bypass diode 104, a larger number of solar cells 102 will be required to produce a given amount of power. The assembly also uses a large metallization area, namely 120 and 122, which makes processing the assembly 100 more difficult, and reduces the yield because of the failures of the interconnections 120 and 122.
It can be seen that there is a need in the art for a solar cell that has an integrated bypass diode. It can also be seen that there is a need in the art for a solar cell that has a bypass diode that minimizes the need for additional wiring and/or metallization interconnects. It can also be seen that there is a need in the art for a bypass diode that minimizes the weight and failure points for solar cell devices.
To address the requirements described above, the present invention discloses a method, and apparatus for providing a bypass diode and solar cell string assembly. The assembly is monolithic and uses standardized semiconductor processing techniques to produce a bypass diode on the solar cell substrate.
The method comprises the steps of depositing a second layer having a first type of dopant on a first layer having an opposite type of dopant to the first type of dopant to form a solar cell, depositing a third layer having the first type of dopant on the second layer, depositing a fourth layer having the opposite type of dopant on the third layer, the third layer and fourth layer forming a bypass diode, selectively etching the third layer and the fourth layer to expose the second layer and the third layer, and applying contacts to the fourth layer, third layer, and the first layer to allow electrical connections to the assembly.
The apparatus comprises a first layer having a first type of dopant, a second layer having a second type of dopant opposite to the first type of dopant, wherein the first layer and the second layer form a solar cell, a third layer, coupled to the second layer, and a fourth layer, coupled to the third layer, the third layer and the fourth layer forming a bypass diode.
The present invention provides a solar cell that has an integrated bypass diode. The present invention also provides a solar cell that has a bypass diode that minimizes the need for additional wiring and/or metallization interconnects, as well as minimizing the weight and failure points for solar cell devices.